Parametric Architecture for Implementing Multimedia Algorithms

Multimedia applications are characterized by high computational demands related to data transfer and storage operations. Multimedia algorithms in their majority consist of regular repetitive loop constructs. In this paper, a novel control architecture for implementing such loop intensive algorithms is described. The proposed control unit takes advantage of the regularity of computations in order to serve as high performance parametric controller of multimedia datapaths. The control unit cooperates with datapath modules and their corresponding controlling FSMs. Algorithmic flow dependencies which determine the appropriate loop sequencing are mapped on a LUT. For another algorithm to execute, LUT context and FSM configurations only have to be reprogrammed. Thus, partial reconfiguration possibilities for implementing multimedia algorithms on programmable platforms can be exploited. For demonstration purposes, a matrix multiply algorithm implementation case is investigated. Compared to a software realization on ARM7 processor, significant performance improvements are reported.